GaN Devices With Ion Implanted Ohmic Contacts and Method of Fabricating Devices Incorporating the Same

ABSTRACT

A method for activating implanted dopants and repairing damage to dopant-implanted GaN to form n-type or p-type GaN. A GaN substrate is implanted with n- or p-type ions and is subjected to a high-temperature anneal to activate the implanted dopants and to produce planar n- or p-type doped areas within the GaN having an activated dopant concentration of about 10 18 -10 22  cm −3 . An initial annealing at a temperature at which the GaN is stable at a predetermined process temperature for a predetermined time can be conducted before the high-temperature anneal. A thermally stable cap can be applied to the GaN substrate to suppress nitrogen evolution from the GaN surface during the high-temperature annealing step. The high-temperature annealing can be conducted under N 2  pressure to increase the stability of the GaN. The annealing can be conducted using laser annealing or rapid thermal annealing (RTA).

CROSS-REFERENCE

This application is a Divisional of and claims the benefit of priorityunder 35 U.S.C. § 120 based on U.S. patent application Ser. No.16/927,061 filed on Jul. 13, 2020, which is a Nonprovisional of andclaims the benefit of priority under 35 U.S.C. § 119 based onProvisional U.S. Patent Application No. 62/878,766 filed on Jul. 26,2019. The prior applications and all cited references are herebyincorporated by reference into the present disclosure in their entirety.

FEDERALLY-SPONSORED RESEARCH AND DEVELOPMENT

The United States Government has ownership rights in this invention.Licensing inquiries may be directed to Office of Technology Transfer, USNaval Research Laboratory, Code 1004, Washington, D.C. 20375, USA;+1.202.767.7230; techtran@nrl.navy.mil, referencing Navy Case #111399.

TECHNICAL FIELD

The present disclosure relates to GaN-based electronic devices, and inparticular to ion-implanted ohmic contacts to such GaN-based devices andmethods for fabricating lateral and vertical electronic devicesincorporating such ion-implanted ohmic contacts.

BACKGROUND

GaN is a superior material for the fabrication of high frequency andhigh power devices. The high electron mobility transistor (HEMT) hasproven to be a groundbreaking technology for RF power amplifiers forboth civilian and defense applications. To achieve high power densityand high efficiency in such devices, extremely low resistance ohmiccontacts are required for the source and drain region of the transistor.The present industry standard for fabrication of low resistance ohmiccontacts is the selective area regrowth method, which can form highlyconductive N+ GaN regions.

However, ion implantation offers several advantages over the selectivearea regrowth method. Ion implantation reduces the number of steps inthe fabrication process, prevents impurity formation from occurring atthe implant/regrowth interface, allows the process to make the devicetruly planar thus reducing the number of critical field points, andallows tailoring of both vertical and lateral profile doping. The cycletime required for ion implantation and activation annealing is much lessthan for epitaxial growth, multiple wafers can be run at the same time,thus substantially improving throughput, and the identical process canbe applied to both Ga-polar and N-polar structures without any specialmodifications. In addition, lateral devices such as photoconductiveswitches and p-n junction gated field effect transistors (LJFET), aswell as vertical devices such as p-n junction gated field effecttransistors (JFET), current aperture vertical electron transistors(CAVET), double diffused metal oxide semiconductor field effecttransistors (DMOS), and trench MOSFET devices could all also potentiallyutilize this technology, since selective-area doping is required for allof these devices.

Ion implantation is the industry standard method for doping Si and SiCdevices. However, since activation of ion implants in GaN requirestemperatures above the decomposition temperature, this method is notpresently used commercially for GaN-based devices. Previous work byresearchers at the Naval Research Laboratory, including some of theinventors of the present invention, has demonstrated that Mg ionimplantation is possible through a symmetric multicycle rapid thermalannealing (SMRTA) and that Mg ion implantation through the SMRTA processcan make p-type GaN. See J. D. Greenlee et al., “Comparison of AlNEncapsulants for Bulk GaN Multicycle Rapid Thermal Annealing,” ECSJ.Solid State Sci. Technol. 4, P 403-P 407 (2015); M. J. Tadjer, et al.,“Selective p-type Doping of GaN:Si by Mg Ion Implantation and MulticycleRapid Thermal Annealing,” ECS J. Solid State Sci. Technol. 5, P 124-P127 (2016

The SMRTA process includes an annealing sequence consisting of periodsof annealing at conventional annealing temperatures with spikes tometastable temperature regimes, combined with the application ofnitrogen overpressure to stabilize the GaN crystal and increase thetemperature at which it can be annealed as well as placement of athermally stable cap on the upper surface of the GaN crystal to protectits surface from dissociating into Ga and N at the high metastableannealing temperatures. See U.S. Pat. No. 8,518,808 to Feigelson et al.,“Defects Annealing and Impurities Activation in III-Nitride Compound,”U.S. Pat. No. 9,543,168 to Feigelson et al., “Defects Annealing andImpurities Activation in Semiconductors at Thermodynamically Non-StableConditions,” and U.S. Patent Application Publication No. 2019/0341261,“Implanted Dopant Activation for Wide Bandgap SemiconductorElectronics,” all of which share at least one inventor in common withthe present disclosure.

SUMMARY

This summary is intended to introduce, in simplified form, a selectionof concepts that are further described in the Detailed Description. Thissummary is not intended to identify key or essential features of theclaimed subject matter, nor is it intended to be used as an aid indetermining the scope of the claimed subject matter. Instead, it ismerely presented as a brief overview of the subject matter described andclaimed herein.

The present invention provides epitaxial GaN devices having highly dopedion-implanted n- or p-type contact regions under metal contacts, wherethe contact regions have activated dopant concentrations of from about10¹⁸ cm⁻³ to about 10²² cm⁻³ or more and where the doped regions areplanar to the epitaxial GaN surface, and further provides methods foractivating implanted dopants and repairing damage to dopant-implantedGaN so as to form the n-type or p-type regions in GaN.

To form n-type regions in GaN, a GaN substrate is masked and the exposedareas are implanted with n-type ions such as Si or Ge. The n-implantedGaN is annealed at high temperatures to activate the implanted n-typedopants, i.e., to produce electrical carriers in the material and toproduce planar areas of activated n-type GaN within the GaN substrate.In some embodiments, the ion-implanted GaN can optionally be subjectedto a first annealing at temperatures at which the GaN remains stable. Insome embodiments, a thermally stable cap can be applied to the GaNsubstrate to suppress nitrogen evolution from the GaN surface during thehigh-temperature annealing, while in other embodiments, thehigh-temperature annealing can be conducted under moderate N₂ pressureto increase the stability of the GaN and reduce the evolution of the N₂from the GaN. In still other embodiments, the annealing can be conductedusing transient annealing techniques such as laser annealing or rapidthermal annealing (RTA) to reduce exposure of GaN to a metastableregime.

To form p-type GaN regions, a GaN substrate is masked and the exposedareas are implanted with p-type ions such as Mg or Be. The p-implantedGaN is then first annealed at temperatures at which the GaN remainsstable and then is annealed at high temperatures to activate theimplanted p-type dopants, i.e., to produce electrical carriers in thematerial and to produce planar areas of activated p-type GaN within theGaN substrate. In some embodiments, a thermally stable cap can beapplied to the GaN substrate to suppress nitrogen evolution from the GaNsurface during the high-temperature annealing step, while in otherembodiments, the high-temperature annealing can be conducted undermoderate N₂ pressure to increase the stability of the GaN and reduce theevolution of the N₂ from the GaN. In still other embodiments, theannealing can be conducted using transient annealing techniques such aslaser annealing or rapid thermal annealing (RTA) to reduce exposure ofGaN to a metastable regime.

Ohmic contacts can then be formed on the n- or p-type areas of the GaNas appropriate to form vertical or lateral electrical devices such asJFETs, CAVETs, DMOS devices, MOSFET devices, HEMT devices, or PCSSdevices.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a plot illustrating aspects of vapor pressure of nitrogen overGaN under a range of temperatures.

FIGS. 2A-2H provide a flow diagram illustrating exemplary process stepsin a method for forming ion-implanted GaN ohmic contacts and forfabricating electronic devices incorporating such ion-implanted GaNohmic contacts in accordance with the present invention.

FIGS. 3A and 3B are photographic images illustrating damage caused bythermal annealing GaN above the thermal decomposition limit when aprotective cap is not used cap (FIG. 3A) and reduced damage when aprotective cap is used (FIG. 3B).

FIG. 4 is a plot illustrating spectral broadening observed of the RamanA₁(LO) peak indicating damage to a GaN sample incurred due to ionimplantation and subsequent recovery after the sample is annealed athigh temperatures.

FIGS. 5A-5C are plots illustrating electrical properties of unannealedion-implanted GaN samples and ion-implanted GaN sample that have beenannealed in accordance with the present invention.

DETAILED DESCRIPTION

The aspects and features of the present invention summarized above canbe embodied in various forms. The following description shows, by way ofillustration, combinations and configurations in which the aspects andfeatures can be put into practice. It is understood that the describedaspects, features, and/or embodiments are merely examples, and that oneskilled in the art may utilize other aspects, features, and/orembodiments or make structural and functional modifications withoutdeparting from the scope of the present disclosure.

The present invention provides epitaxial GaN devices having highly dopedion-implanted n- or p-type contact regions under metal contacts, wherethe contact regions have activated dopant concentrations of about 10¹⁸cm⁻³ to about 10²² cm⁻³ and where the doped regions are planar to theepitaxial GaN surface, and further provides methods for activatingimplanted dopants and repairing damage to dopant-implanted GaN so as toform the n-type or p-type regions in GaN.

The activated ion-implanted n-type and p-type regions in GaN can be isachieved using components of the SMRTA process developed by inventors atNRL to create n-type or p-type GaN using ion implantation of Si orother-dopants into GaN. N-type dopants are significantly more abundantin the GaN materials system, exhibit lower electrical activation energythan p-type dopants and can be activated at lower temperatures. Thus,while the use of overpressure and application of a thermally stable capsuch as is used in the SMRTA process greatly facilitates dopantactivation, the temperature spikes to metastable temperature regimesused in the SMRTA process is not necessary to activate n-type dopants,nor is pressure always necessary to activate n-type dopants.

Implantation of n- or p-type dopants in accordance with the presentinvention can be performed on unintentionally doped GaN, semi-insulatingGaN such as carbon doped GaN, or on AlGaN/GaN heterostructures situatedon GaN, SiC, Si, sapphire, or composite engineered substrates.

Implantation of dopants into GaN damages the lattice structure of theGaN crystal and causes it to have low mobility and become highlyresistive. To repair this lattice damage after implantation and activatethe implanted dopant impurities, the GaN structure must be annealed,with the annealing taking place at high temperatures at which theion-implanted GaN crystal is metastable at atmospheric pressure, i.e.,above the equilibrium thermal decomposition limit of about 850° C., allthe while maintaining the structural integrity of the GaN crystal. Theannealing temperature required to activate the implanted dopants andrepair the damage caused by the dopant implantation is typically in the900-1600° C. range for n-type dopants and 1200-1600° C. range for p-typedopants.

However, as can be seen from the phase diagram shown in FIG. 1, GaNdecomposes into its constituent elements Ga+N when heated toapproximately 850° C. at atmospheric pressure. Mitigation of thisdecomposition is critical since nitrogen vacancies and other complexesformed by the decomposition cause leakage paths and degrade deviceperformance.

Thus, in accordance with the present invention, the ion-implanted GaNmust be protected during this metastable annealing to properly activatedopants and mitigate damage to the device structure. This protection ofthe GaN can be achieved by any one or a combination of the followingapproaches developed by the inventors as part of the SMRTA techniquedescribed in U.S. Pat. Nos. 8,518,808, 9,543,168, and U.S. PatentApplication Publication No. 2019/0341261, supra.

An exemplary process flow for forming highly doped activatedion-implanted planar n-type regions in GaN in accordance with thepresent invention is illustrated by the block schematics shown in FIGS.2A-2H.

As shown in FIG. 2A, the process begins with the deposition of a GaNfilm 202 on a SiC substrate 201, where the GaN film can be formed by anysuitable technique known in the art such as MOCVD, HVPE, or MBE. The GaNcan optionally be initially doped with carbon (with the GaN thus beingdenoted as S.I. GaN:C in the FIGURES) to make it semi-insulating.

In a second step in a process for fabricating an electronic deviceincorporating n-type GaN in accordance with the present invention, asillustrated in FIG. 2B, a sacrificial mask 203, e.g., a mask fromstandard photolithography photoresist or a hard mask, is deposited on anupper surface of the GaN to protect areas of the sample which are not tobe implanted by Si. In a third step, illustrated in FIG. 2C, photomask203 is selectively removed to expose regions 204 of the GaN to beimplanted with n-type dopants, and the dopants are implanted into theexposed regions of the GaN to form doped regions 205, where implantationcan be accomplished using any suitable implantation tool known in theart. Following implantation, in the next step, the mask is removed, asillustrated in FIG. 2D, to expose the GaN surface for furtherprocessing.

In one approach, aspects of which are illustrated in FIG. 2E, one ormore thermally stable caps 206 can be applied to the upper surface ofthe n-implanted GaN to suppress nitrogen evolution from the GaN surface.The cap can comprise AlN, SiN, or other stable materials or compositestructures of multiple materials are capable of protecting the crystalfrom decomposition.

In another approach, moderate Na pressure can be applied duringannealing with the Na pressure increasing the stability of the GaN andreducing the evolution of Na from the GaN crystal. Application of an Naoverpressure of up to about 100 bar in combination with use of aprotective cap has been shown to stabilize the GaN at temperaturesexceeding 1200° C. for short times.

In still another approach, transient annealing techniques such as laserannealing or rapid thermal annealing (RTA) can be used to reduceexposure of GaN to a metastable regime and kinetically limitdecomposition or nitrogen evolution. See U.S. Pat. Nos. 8,518,808 and9,543,168, supra; see also U.S. Patent Application Publication No.2019/0341261, supra.

Irrespective of the approach used for this high-temperature annealing,it has been found that improved annealing of the n-implanted GaN canoften be achieved by means of an optional first annealing step, wherethe n-implanted GaN is initially annealed for a predetermined period oftime at a predetermined temperature when GaN is still stable before itis annealed at metastable temperatures. This initial stable annealingreduces the initial defect populations in the GaN and improves itstolerance of metastable annealing. See J. D. Greenlee et al., “Processoptimization of multicycle rapid thermal annealing of Mg-implanted GaN,”2014 IEEE Workshop on Wide Bandgap Power Devices and Applications,Knoxville, Tenn., 2014, pp. 59-62; see also J. D. Greenlee et al., “FromMRTA to SMRTA: Improvements in Activating Implanted Dopants in GaN,” ECSTransactions 69(14):97-102. The specific time and temperature of thisinitial stable annealing can be tailored to the maximum temperature atwhich the GaN is stable at the process pressure and for durationsnecessary to improve resultant GaN mobility or activation, but typicallyis done below about 850° C. under atmospheric pressure for up to severalhours but can be done at up to 1050° C. for a few seconds.

In the next step of a process for fabricating an electronic deviceincorporating ion-implanted GaN in accordance with the presentinvention, as illustrated in FIG. 2F the n-implanted GaN is thenannealed at high temperatures to activate the implanted n-type dopants,i.e., to produce electrical carriers in the material and to produceactivated planar n-type regions 207 within the GaN. Such annealing istypically conducted at temperatures of about 900 to about 1600° C. andat pressures ranging from 1 atm to about 100 bar. The annealing time inthis step can vary from a few seconds to about an hour, with highertemperatures needing less time.

If a protective cap was applied to protect the GaN surface from damageduring the metastable annealing, in the next step of a process forfabricating an electronic device incorporating regions of n-type GaN inaccordance with the present invention, as illustrated in FIG. 2G, theprotective cap is then removed to expose the annealed n-type areas inthe GaN, where removal can be achieved using any suitable method knownin the art, such as by means of plasma etching or by means of chemicaletching using hydrofluoric acid (HF), potassium hydroxide (KOH), or theAZ400K developer available from AZ Industries.

Finally, as illustrated in FIG. 2H, ohmic contacts 208 a/208 b aredeposited on an upper surface of the n-GaN areas of the GaN crystal,with the material and placement of the contacts being configured asappropriate for the specific device structure and design considerations.

The implantation and annealing process in accordance with the presentinvention results in a GaN substrate with highly n-doped GaN regionshaving an activated n-type dopant concentration of about 10¹⁸ cm⁻³ toabout 10²² cm⁻³, where the doped regions are planar to the epitaxial GaNfilm.

Highly p-doped regions in GaN with activated p-type dopant ions having aconcentration of about 10¹⁸ cm⁻³ to about 10²² cm⁻³ can be similarlyproduced by doping the GaN with p-type dopants such as Mg or Be.However, activation of such p-type dopants typically requires annealingat higher temperatures or for longer durations to further reduce ionimplantation damage.

Producing such highly p-doped regions in GaN typically requires theinitial annealing step that is optional for n-doped GaN, before thedoped GaN is subjected to high temperature annealing, i.e., an initialanneal at a temperature at which GaN is still stable at the processpressure and process time, e.g., below about 850° C. for several hoursat atmospheric pressure or up to about 1050° C. for a few minutes atatmospheric pressure. Following this initial annealing step, the p-dopedGaN is subjected to a metastable annealing regime similar to thatdescribed above with respect to n-doped GaN to activate the implantedp-type dopants, i.e., to produce electrical carriers in the material andto produce activated planar p-type regions within the GaN. As with theannealing of n-doped GaN, such annealing is typically conducted attemperatures of about 1200 to about 1600° C. and at pressures rangingfrom 1 atm to about 100 bar. The annealing time in this step can varyfrom a few seconds to about an hour, with higher temperatures needingless time. The protective measures described above, such as thedeposition of a protective cap or the application of nitrogenoverpressure, can be employed to prevent the GaN from decomposing intoGa and N₂ during this high-temperature annealing.

The result of the annealing process in accordance with the presentinvention is a GaN substrate which has one or more regions having a high(10¹⁸ cm⁻³ to about 10²² cm⁻³) concentration of activated p-typedopants, where the highly doped regions are planar to the epitaxial GaNsurface.

As noted above, one way to protect the GaN from decomposing into itsconstituent elements during the metastable annealing step is to deposita thermally stable cap onto the GaN surface. The beneficial effects ofusing such a cap can be seen from the images shown in FIGS. 3A and 3B.FIG. 3A shows the surface of an ion-implanted GaN sample and showsmultiple areas where the surface of the GaN is damaged. In contrast, theGaN sample shown in FIG. 3B was protected by a cap duringhigh-temperature metastable annealing in accordance with the presentinvention, and as can be seen from FIG. 3B, is free from any visibledefects.

As noted above, the annealing temperature required to activate theimplanted dopants and repair the damage caused by the dopantimplantation is typically in the 900-1600° C. range for n-type dopantsand 1200-1600° C. range for p-type dopants. The benefits of thishigh-temperature annealing can be seen from the plots in FIG. 4. Thecrystal damage caused by n-dopant implantation can be observed using theAi peak in a Raman spectra, as illustrated by the plots in FIG. 4A. Thedotted line 401 in FIG. 4 shows the Raman peak for a raw, unimplantedsample. After n-dopant implantation, the Raman peak broadens (line 402),indicating Raman dispersion from implant-induced vacancies and damage.Annealing at both 1150° C. (403) and 1180° C. (404) narrows the width ofthe Raman peak to bring it closer to the peak shown by the unimplantedsample, indicating recovery of the damage to the GaN crystal introducedby ion implantation.

The results of annealing under different conditions are shown by theplots in FIGS. 5A-5C. The plot in FIG. 5A shows that the resistivity ofan n-doped GaN sample drops as the annealing temperature increases untilit reaches a minimum above an annealing temperature of around 1050° C.This minimum resistivity also corresponds to a minimum in contactresistivity in the 10⁻⁶ Ω-cm scale, as seen by the plot in FIG. 5B,which illustrates that low contact resistance, beyond that exhibited byboth unimplanted and unannealed samples, can be obtained after theimplanted samples are annealed.

The impact of the annealing process on the unimplanted regions isequally important to device operation as these must remain capable ofsustaining high electric field. To this end, any additional damageintroduced by decomposition of the crystal is critical. The plot in FIG.5C illustrates the current traveling through unimplanted regions of theGaN sample between implanted contacts as a function of voltage fordevices annealed at different temperatures (plot lines 501-506) for 5minutes at 30 atm pressure fabricated as described above with respect toFIGS. 1A-1H. The reference curve 507 for a device fabricated fromunimplanted and unannealed GaN shows a breakdown around 3000 V. As canbe seen from the plots in FIG. 5C, annealing under non-optimizedconditions, either too cold to reduce the ion implantation damage (lines501 and unannealed 508) or too hot, which generates additional defects(lines 503, 504, 505, 506) decreases breakdown voltage and increasesleakage current by at least a factor of 2, under more optimal conditionsof annealing near 1050° C. (line 502) the breakdown voltage increasesbeyond that exhibited by the as-grown, unimplanted, unannealed material.

The highly doped planar ion-implanted n- and p-type GaN produced by theimplantation and annealing process in accordance with the presentinvention can be incorporated into many different electronic devicesknown in the art, including vertical devices such as JFETs, CAVETs, DMOSdevices, and MOSFET devices and lateral devices such as HEMTs and PCSSdevices,

All of these devices can be synthesized with fewer processing steps byusing the n-type ion implantation technique and annealing processes ofthe present invention. Most notably though, this process can be used tosignificantly simplify the contact process in both Ga-polar and N-polarHigh Electron Mobility Transistors (HEMTs) as described above byobviating the need for regrowth of contacts, thus eliminating a slow andcostly step as well as removing an interface which causes leakage andbreakdown pathways. Another significant aspect of the process of thepresent invention is that it can potentially be performed in a foundrywith modifications to the fabrication sequence and/or process tools.

A method for activating implanted dopants and repairing damage caused bythe dopant implantation has been described. Although particularembodiments, aspects, and features have been described and illustrated,one skilled in the art would readily appreciate that the inventiondescribed herein is not limited to only those embodiments, aspects, andfeatures but also contemplates any and all modifications and alternativeembodiments that are within the spirit and scope of the underlyinginvention described and claimed herein. The present applicationcontemplates any and all modifications within the spirit and scope ofthe underlying invention described and claimed herein, and all suchmodifications and alternative embodiments are deemed to be within thescope and spirit of the present disclosure.

What is claimed is:
 1. An epitaxial GaN substrate having at least oneselectively formed activated n-type doped region therein; wherein theactivated n-type doped region is planar to a surface of the epitaxialGaN substrate and has a concentration of electrically activatedion-implanted n-type dopants of about 10¹⁸ cm⁻³ to about 10²² cm⁻³. 2.The epitaxial GaN substrate according to claim 1, wherein the n-typedopants are Si or Ge.
 3. An epitaxial GaN substrate having at least oneselectively formed activated p-type doped region therein; wherein theactivated p-type doped region is planar to a surface of the epitaxialGaN substrate and has a concentration of electrically activatedion-implanted p-type dopants of about 10¹⁸ cm⁻³ to about 10²² cm⁻³. 4.The epitaxial GaN substrate according to claim 3, wherein the p-typedopants are Mg or Be.